xapp1018_wcdma\ddc
..............\...\Implementation
..............\...\..............\Sp3a
..............\...\..............\....\ddc_umts_sp3a_init.m
..............\...\..............\....\ddc_umts_sp3a_post.m
..............\...\..............\....\ddc_umts_sp3a_v1_0.mdl
..............\...\..............\....\readme.txt
..............\...\..............\VHDL
..............\...\..............\....\complex_mult_v5.vhd
..............\...\..............\....\cores
..............\...\..............\....\.....\ddc_hf1
..............\...\..............\....\.....\.......\ddc_h1.coe
..............\...\..............\....\.....\.......\ddc_hf1.edn
..............\...\..............\....\.....\.......\ddc_hf1.mif
..............\...\..............\....\.....\.......\ddc_hf1.vhd
..............\...\..............\....\.....\.......\ddc_hf1.vho
..............\...\..............\....\.....\.......\ddc_hf1.xco
..............\...\..............\....\.....\.......\ddc_hf1COEFF_auto0.mif
..............\...\..............\....\.....\.......\ddc_hf1COEFF_auto_HALFBAND_CENTRE.mif
..............\...\..............\....\.....\.......\ddc_hf1filt_decode_rom.mif
..............\...\..............\....\.....\.......\ddc_hf1_fir_compiler_v3_0_xst_1.ngc
..............\...\..............\....\.....\.......\ddc_hf1_flist.txt
..............\...\..............\....\.....\.......\ddc_hf1_readme.txt
..............\...\..............\....\.....\.......\ddc_hf1_unobf.ngc
..............\...\..............\....\.....\.......\ddc_hf1_xmdf.tcl
..............\...\..............\....\.....\.......\hex_ddc_hf1.mif
..............\...\..............\....\.....\ddc_hf2
..............\...\..............\....\.....\.......\ddc_h2.coe
..............\...\..............\....\.....\.......\ddc_hf2.edn
..............\...\..............\....\.....\.......\ddc_hf2.mif
..............\...\..............\....\.....\.......\ddc_hf2.vhd
..............\...\..............\....\.....\.......\ddc_hf2.vho
..............\...\..............\....\.....\.......\ddc_hf2.xco
..............\...\..............\....\.....\.......\ddc_hf2COEFF_auto0.mif
..............\...\..............\....\.....\.......\ddc_hf2COEFF_auto_HALFBAND_CENTRE.mif
..............\...\..............\....\.....\.......\ddc_hf2filt_decode_rom.mif
..............\...\..............\....\.....\.......\ddc_hf2_fir_compiler_v3_0_xst_1.ngc
..............\...\..............\....\.....\.......\ddc_hf2_flist.txt
..............\...\..............\....\.....\.......\ddc_hf2_readme.txt
..............\...\..............\....\.....\.......\ddc_hf2_unobf.ngc
..............\...\..............\....\.....\.......\ddc_hf2_xmdf.tcl
..............\...\..............\....\.....\.......\hex_ddc_hf2.mif
..............\...\..............\....\.....\ddc_srrc
..............\...\..............\....\.....\........\ddc_h3.coe
..............\...\..............\....\.....\........\ddc_srrc.edn
..............\...\..............\....\.....\........\ddc_srrc.mif
..............\...\..............\....\.....\........\ddc_srrc.vhd
..............\...\..............\....\.....\........\ddc_srrc.vho
..............\...\..............\....\.....\........\ddc_srrc.xco
..............\...\..............\....\.....\........\ddc_srrcCOEFF_auto0.mif
..............\...\..............\....\.....\........\ddc_srrcCOEFF_auto1.mif
..............\...\..............\....\.....\........\ddc_srrcfilt_decode_rom.mif
..............\...\..............\....\.....\........\ddc_srrc_fir_compiler_v3_0_xst_1.ngc
..............\...\..............\....\.....\........\ddc_srrc_flist.txt
..............\...\..............\....\.....\........\ddc_srrc_readme.txt
..............\...\..............\....\.....\........\ddc_srrc_unobf.ngc
..............\...\..............\....\.....\........\ddc_srrc_xmdf.tcl
..............\...\..............\....\.....\........\hex_ddc_srrc.mif
..............\...\..............\....\.....\dds
..............\...\..............\....\.....\...\ddc_dds_v5.edn
..............\...\..............\....\.....\...\ddc_dds_v5.vhd
..............\...\..............\....\.....