Description: Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this module.
- [da] - Realize da conversion feature, not very
- [readme_vhd] - SERDES VHDL source code, you can achieve
- [Signal] - Used VerilogHDL to make a frequency buil
- [DA] - FPGA control DAC2807 source, Verilog. A
- [AD] - FPGA implementation of the AD sampling c
- [frame_synchronization] - Detection of Barker code transmission to
- [C51_module] - C51 programming accumulated a small modu
File list (Check if you may need any files):
DAx_module.vhd
DAy_module.vhd
mySPI_receive_top.vhd
osc_top.vhd
PCMP.vhd
pll_20.vhd
ram_2port.vhd
ram_3port.vhd
Ram_rclk.vhd
ReadRam_module.vhd
sipo.vhd
tri_module.vhd
WriteRam_module.vhd
clk_control.vhd
clk_div2.vhd
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