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Title: basedonFPGALCD Download
 Description: FPGA-based LCD interface program code, you can run the xilinx or altera Development Board
 Downloaders recently: [More information of uploader ren_cc]
File list (Check if you may need any files):
基于FPGA的LCD接口程序\vga_lcd\bench\CVS\Entries
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.....................\.......\.....\.......\sync_check.v
.....................\.......\.....\.......\tests.v
.....................\.......\.....\.......\test_bench_top.v
.....................\.......\.....\.......\wb_b3_check.v
.....................\.......\.....\.......\wb_mast_model.v
.....................\.......\.....\.......\wb_model_defines.v
.....................\.......\.....\.......\wb_slv_model.v
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.....................\.......\doc\CVS\Entries
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.....................\.......\...\src\CVS\Entries
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.....................\.......\...\...\vga_core_enh.doc
.....................\.......\...\vga_core.pdf
.....................\.......\rtl\CVS\Entries
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.....................\.......\...\hdl\CVS\Entries
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.....................\.......\...\verilog\CVS\Entries
.....................\.......\...\.......\...\Repository
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.....................\.......\...\.......\generic_dpram.v
.....................\.......\...\.......\generic_spram.v
.....................\.......\...\.......\timescale.v
.....................\.......\...\.......\vga_clkgen.v
.....................\.......\...\.......\vga_colproc.v
.....................\.......\...\.......\vga_csm_pb.v
.....................\.......\...\.......\vga_curproc.v
.....................\.......\...\.......\vga_cur_cregs.v
.....................\.......\...\.......\vga_defines.v
.....................\.......\...\.......\vga_enh_top.v
.....................\.......\...\.......\vga_fifo.v
.....................\.......\...\.......\vga_fifo_dc.v
.....................\.......\...\.......\vga_pgen.v
.....................\.......\...\.......\vga_tgen.v
.....................\.......\...\.......\vga_vtim.v
.....................\.......\...\.......\vga_wb_master.v
.....................\.......\...\.......\vga_wb_slave.v
.....................\.......\...\.hdl\colproc.vhd
.....................\.......\...\....\counter.vhd
.....................\.......\...\....\csm_pb.vhd
.....................\.......\...\....\CVS\Entries
.....................\.......\...\....\...\Repository
.....................\.......\...\....\...\Root
.....................\.......\...\....\dpm.vhd
.....................\.......\...\....\fifo.vhd
.....................\.......\...\....\fifo_dc.vhd
.....................\.......\...\....\pgen.vhd
.....................\.......\...\....\tgen.vhd
.....................\.......\...\....\vga.vhd
.....................\.......\...\....\vga_and_clut.vhd
.....................\.......\...\....\vga_and_clut_tstbench.vhd
.....................\.......\...\....\vtim.vhd
.....................\.......\...\....\wb_master.vhd
.....................\.......\...\....\wb_slave.vhd
.....................\.......\sim\CVS\Entries
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.....................\.......\...\rtl_sim\bin\CVS\Entries
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.....................\.......\...\.......\...\Makefile
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.....................\.......\...\.......\...\Repository
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.....................\.......\...\.......\run\CVS\Entries
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