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Title: adc_sensor Download
 Description: adc is fpga latform code for testing temparature sense
 Downloaders recently: [More information of uploader mar.rhl]
 To Search: fpga ADC
  • [FPGA_27eg] - FPGA value of the 27 examples. Rar inclu
  • [FPGAAD] - FPGA control AD procedure
  • [adc_vhdl.tar] - control adc vhdl code spartan 3e starter
File list (Check if you may need any files):
adc_sensor\.lso
..........\adc.prj
..........\adc.stx
..........\adc.v
..........\adc.xst
..........\adc_sensor.ise
..........\adc_sensor.ise_ISE_Backup
..........\adc_sensor.restore
..........\adc_summary.html
..........\pressure.prj
..........\pressure.stx
..........\pressure.v
..........\pressure.xst
..........\speed.prj
..........\speed.stx
..........\speed.v
..........\speed.xst
..........\temparature.prj
..........\temparature.stx
..........\temparature.v
..........\temparature.xst
..........\test.ant
..........\test.fdo
..........\test.jhd
..........\test.tbw
..........\test.udo
..........\test.xwv
..........\test.xwv_bak
..........\test1.ant
..........\test1.fdo
..........\test1.jhd
..........\test1.tbw
..........\test1.udo
..........\test1.xwv
..........\test1.xwv_bak
..........\test2.ant
..........\test2.fdo
..........\test2.jhd
..........\test2.tbw
..........\test2.udo
..........\test2.xwv
..........\test2.xwv_bak
..........\test2_bencher.prj
..........\test3.ant
..........\test3.fdo
..........\test3.jhd
..........\test3.tbw
..........\test3.tfw
..........\test3.udo
..........\test3.xwv
..........\test3.xwv_bak
..........\test3_bencher.prj
..........\test_bencher.prj
..........\transcript
..........\vsim.wlf
..........\work\adc\verilog.psm
..........\....\...\_primary.dat
..........\....\...\_primary.vhd
..........\....\glbl\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\pressure\verilog.psm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\speed\verilog.psm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\temperature\verilog.psm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\..st\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\....1\verilog.psm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\....2\verilog.psm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\....3\verilog.psm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\_info
..........\xst\work\hdllib.ref
..........\...\....\vlg11\pressure.bin
..........\...\....\...2D\speed.bin
..........\...\....\....E\temparature.bin
..........\...\....\...50\adc.bin
..........\...\....\....2\temperature.bin
..........\_xmsgs\xst.xmsgs
..........\xst\work\vlg11
..........\...\....\vlg2D
..........\...\....\vlg2E
..........\...\....\vlg50
..........\...\....\vlg52
..........\work\adc
..........\....\glbl
..........\....\pressure
..........\....\speed
..........\....\temperature
    

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