Description: Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal)
File list (Check if you may need any files):
5956447divider\divider\divider.v
..............\.......\div_ctl.v
..............\.......\div_datapath.v
..............\.......\div_tb.v
..............\.......\read me.txt
..............\divider
5956447divider
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