Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: au Download
 Description: UART controller based on AMBA APB
 Downloaders recently: [More information of uploader xusamuel]
 To Search: apb uart amba APB
  • [veriloghdl] - VERILOG courseware taught by germans who
  • [ram_ahbif] - This is a amba bus control
  • [apb_slave] - AMBA 2.0 APB Example- SRAM
  • [AHB_QUESTIONS] - AMBA AHB Interview Questions
  • [113] - Q & A article rookie Yi language ques
  • [114] - Yi language courses, three minutes to le
  • [AHBtoAPB] - amba bus bridge: ahb to asb! verilog hdl
File list (Check if you may need any files): 
au\.restartSimSession.tcl.old
..\.vcsmx_rebuild
..\sim\nc\.vcsmx_rebuild
..\...\vcs\vcsd
..\.rc\verilog\au.v
..\.yn\synplify\.recordref
..\tb\au_tb.v
..\doc\design
..\...\verification
..\sim\modelsim
..\...\nc
..\...\vcs
..\.rc\verilog
..\...\vhdl
..\.yn\ise
..\...\synopsys
..\...\synplify
..\c
..\doc
..\sim
..\src
..\syn
..\tb
au

CodeBus www.codebus.net