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Title: verilogclk Download
 Description: Verilog HDL language multi-function digital clock.
 Downloaders recently: [More information of uploader 502297805]
 To Search:
  • [NumClock] - based Altera FPGA series (Cyclone EP1C3T
  • [shuzizhong] - The design of a can be hours, minutes, s
  • [szz] - Digital clock written in Verilog, the us
File list (Check if you may need any files):
多功能数字钟源码(verilog)\多功能数字钟\clk.bsf
...........................\............\clk.v
...........................\............\CLK.vwf
...........................\............\cmp_state.ini
...........................\............\ct.bsf
...........................\............\ct.v
...........................\............\ct.vwf
...........................\............\ct1.vwf
...........................\............\db\add_sub_1sh.tdf
...........................\............\..\add_sub_eth.tdf
...........................\............\..\add_sub_vrh.tdf
...........................\............\..\cntr_2c7.tdf
...........................\............\..\cntr_e08.tdf
...........................\............\..\work.asm.qmsg
...........................\............\..\work.cmp.cdb
...........................\............\..\work.cmp.ddb
...........................\............\..\work.cmp.hdb
...........................\............\..\work.cmp.rdb
...........................\............\..\work.cmp.tdb
...........................\............\..\work.cmp0.ddb
...........................\............\..\work.db_info
...........................\............\..\work.eco.cdb
...........................\............\..\work.eds_overflow
...........................\............\..\work.fit.qmsg
...........................\............\..\work.fnsim.cdb
...........................\............\..\work.fnsim.hdb
...........................\............\..\work.hier_info
...........................\............\..\work.hif
...........................\............\..\work.icc
...........................\............\..\work.map.cdb
...........................\............\..\work.map.hdb
...........................\............\..\work.map.qmsg
...........................\............\..\work.pre_map.cdb
...........................\............\..\work.pre_map.hdb
...........................\............\..\work.psp
...........................\............\..\work.rtlv.hdb
...........................\............\..\work.rtlv_sg.cdb
...........................\............\..\work.rtlv_sg_swap.cdb
...........................\............\..\work.sgdiff.cdb
...........................\............\..\work.sgdiff.hdb
...........................\............\..\work.signalprobe.cdb
...........................\............\..\work.sim.hdb
...........................\............\..\work.sim.qmsg
...........................\............\..\work.sim.rdb
...........................\............\..\work.sim.vwf
...........................\............\..\work.sld_design_entry.sci
...........................\............\..\work.sld_design_entry_dsc.sci
...........................\............\..\work.syn_hier_info
...........................\............\..\work.tan.qmsg
...........................\............\..\work_cmp.qrpt
...........................\............\..\work_sim.qrpt
...........................\............\muxtwo.v
...........................\............\muxtwo.vwf
...........................\............\piaobiao.bsf
...........................\............\piaobiao.v
...........................\............\piaobiao.vwf
...........................\............\piaobiao1.vwf
...........................\............\select.bsf
...........................\............\select.v
...........................\............\select.vwf
...........................\............\select2.vwf
...........................\............\work.asm.rpt
...........................\............\work.bdf
...........................\............\work.done
...........................\............\work.fit.eqn
...........................\............\work.fit.rpt
...........................\............\work.fit.summary
...........................\............\work.flow.rpt
...........................\............\work.map.eqn
...........................\............\work.map.rpt
...........................\............\work.map.summary
...........................\............\work.pin
...........................\............\work.pof

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