Description: - logarithm matlab code, verilog code, test bench
- document
- [cordic_vhdl1] - use cordic achieve very Cartesian coordi
- [Calc] - LabVIEW prepared to use a calculator pro
- [1] - c++ realized image matrix logarithm. Whi
- [edge_detection] - edge detection algorithm in verilog HDL,
- [bitload] - A new channel estimation algorithm of th
- [bluetooth] - Bluetooth communication system simulatio
- [Processor_alu] - this Code is in verilog HDL. This Code i
- [cordic_atan] - Calculated using verilog language arc ta
File list (Check if you may need any files):
logarithm\document
.........\........\Log2_LUT_conversion.pdf
.........\natural
.........\.......\in.dat
.........\.......\matlab_simulation
.........\.......\.................\comparison.m
.........\.......\.................\top.asv
.........\.......\.................\top.m
.........\.......\out.dat
.........\.......\RTL_code
.........\.......\........\booth_16_16_2.v
.........\.......\........\booth_16_5.v
.........\.......\........\booth_16_5.v.bak
.........\.......\........\booth_encoder.v
.........\.......\........\log.v
.........\.......\........\log.v.bak
.........\.......\........\log_2.v
.........\.......\........\log_2.v.bak
.........\.......\........\log_temp.v
.........\.......\........\log_temp.v.bak
.........\.......\test_benches
.........\.......\............\a_tb_nat_log.v
.........\.......\............\a_tb_nat_log.v.bak
.........\.......\............\wave.do
.........\.......\vsim.wlf
.........\.......\vsim_stacktrace.vstf
.........\.......\work
.........\.......\....\_info
.........\.......\....\a_tb_nat_log
.........\.......\....\............\_primary.dat
.........\.......\....\............\_primary.vhd
.........\.......\....\............\verilog.asm
.........\.......\....\booth_16_16_2
.........\.......\....\.............\_primary.dat
.........\.......\....\.............\_primary.vhd
.........\.......\....\.............\verilog.asm
.........\.......\....\booth_16_5
.........\.......\....\..........\_primary.dat
.........\.......\....\..........\_primary.vhd
.........\.......\....\..........\verilog.asm
.........\.......\....\booth_encoder
.........\.......\....\.............\_primary.dat
.........\.......\....\.............\_primary.vhd
.........\.......\....\.............\verilog.asm
.........\.......\....\log
.........\.......\....\...\_primary.dat
.........\.......\....\...\_primary.vhd
.........\.......\....\...\verilog.asm
.........\.......\....\log_2
.........\.......\....\.....\_primary.dat
.........\.......\....\.....\_primary.vhd
.........\.......\....\.....\verilog.asm
.........\.......\....\log_temp
.........\.......\....\........\_primary.dat
.........\.......\....\........\_primary.vhd
.........\.......\....\........\verilog.asm
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