Description: In quartus II environment achieved with Verilog 8255, 8253, 8259, 8250, DAC0832, ADC0809 and other computer interface chip, hardware design experiment course of works, some chips have simplified the function, but the most basic functions have been achieved, with complete timing simulation waveform
- [jksydm] - Several interface experimental code. Inc
- [DAC0832] - Single-chip analog-to-digital conversion
- [ADC0809] - ADC0809 conversion process and achieve t
- [AD] - Single-channel voltage converter ADC0809
- [DAC0832] - DAC0832 and simulation of VHDL programs.
- [8253] - 8253 counter interface circuit
- [8259_VHDL_OSED] - 8259 VHDL routines to achieve with alter
- [hly] - proteus，avr atmega lcd1602 dac0832 AD
- [gh_timer_8254_081608] - Timer 8254 Verilog source code
- [Administrator] - dat segment import db input a 4 bit hex:
File list (Check if you may need any files):
pic8259a\8259a.asm.rpt
........\8259a.bdf
........\8259a.done
........\8259a.dpf
........\8259a.fit.rpt
........\8259a.fit.smsg
........\8259a.fit.summary
........\8259a.flow.rpt
........\8259a.map.rpt
........\8259a.map.smsg
........\8259a.map.summary
........\8259a.pin
........\8259a.pof
........\8259a.qsf
........\8259a.sim.cvwf
........\8259a.sim.rpt
........\8259a.sof
........\8259a.tan.rpt
........\8259a.tan.summary
........\8259a.v
........\8259a.v.bak
........\8259a.vwf
........\8259a_assignment_defaults.qdf
........\8259a_down.bdf
........\8259a_down.vwf
........\8259a_down2.bdf
........\8259a_down2.sim.cvwf
........\8259a_down2.vwf
........\core.bsf
........\core.sim.cvwf
........\core.v
........\core.v.bak
........\core.vwf
........\core_down.bdf
........\core_down.bsf
........\core_final.bdf
........\core_final.bsf
........\db\8259a.analyze_file.qmsg
........\..\8259a.asm.qmsg
........\..\8259a.asm_labs.ddb
........\..\8259a.cbx.xml
........\..\8259a.cmp.bpm
........\..\8259a.cmp.cdb
........\..\8259a.cmp.ecobp
........\..\8259a.cmp.hdb
........\..\8259a.cmp.logdb
........\..\8259a.cmp.rdb
........\..\8259a.cmp.tdb
........\..\8259a.cmp0.ddb
........\..\8259a.cmp_bb.cdb
........\..\8259a.cmp_bb.hdb
........\..\8259a.cmp_bb.logdb
........\..\8259a.cmp_bb.rcf
........\..\8259a.dbp
........\..\8259a.db_info
........\..\8259a.eco.cdb
........\..\8259a.eds_overflow
........\..\8259a.fit.qmsg
........\..\8259a.fnsim.hdb
........\..\8259a.fnsim.qmsg
........\..\8259a.hier_info
........\..\8259a.hif
........\..\8259a.map.bpm
........\..\8259a.map.cdb
........\..\8259a.map.ecobp
........\..\8259a.map.hdb
........\..\8259a.map.logdb
........\..\8259a.map.qmsg
........\..\8259a.map_bb.cdb
........\..\8259a.map_bb.hdb
........\..\8259a.map_bb.logdb
........\..\8259a.pre_map.cdb
........\..\8259a.pre_map.hdb
........\..\8259a.psp
........\..\8259a.pss
........\..\8259a.rtlv.hdb
........\..\8259a.rtlv_sg.cdb
........\..\8259a.rtlv_sg_swap.cdb
........\..\8259a.sgdiff.cdb
........\..\8259a.sgdiff.hdb
........\..\8259a.signalprobe.cdb
........\..\8259a.sim.cvwf
........\..\8259a.sim.hdb
........\..\8259a.sim.qmsg
........\..\8259a.sim.rdb
........\..\8259a.sld_design_entry.sci
........\..\8259a.sld_design_entry_dsc.sci
........\..\8259a.syn_hier_info
........\..\8259a.tan.qmsg
........\..\8259a.tis_db_list.ddb
........\..\mux_3nc.tdf
........\..\prev_cmp_8259a.asm.qmsg
........\..\prev_cmp_8259a.fit.qmsg
........\..\prev_cmp_8259a.map.qmsg
........\..\prev_cmp_8259a.sim.qmsg
........\..\prev_cmp_8259a.tan.qmsg
........\..\prev_cmp_pic8259a.qmsg
........\..\wed.wsf
........\hold.bsf
........\hold.v
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