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VHDL-FPGA-Verilog
Title:
dayin
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Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
65kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
rain2660
Description:
The program using vhdl language, using look-up table method to achieve am modulation, this method is simple and effective
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