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Title: shift_reg Download
 Description: Shift register, Verilog implementation, there is experimental documentation.
 Downloaders recently: [More information of uploader ycf128]
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移位寄存器实验例程及文档\shift_reg\designer\impl1\designer.log
........................\.........\........\.....\designer_gen_ba.log
........................\.........\........\.....\shift_reg.adb
........................\.........\........\.....\..........dtf\verify.log
........................\.........\........\.....\shift_reg.ide_des
........................\.........\........\.....\shift_reg.pdb
........................\.........\........\.....\shift_reg.pdb.depends
........................\.........\........\.....\shift_reg.tcl
........................\.........\........\.....\shift_reg_ba.sdf
........................\.........\........\.....\shift_reg_ba.sdf_max.csd
........................\.........\........\.....\shift_reg_ba.v
........................\.........\........\.....\..........fp\$$FlashPro_FPBBALTLPT1.L$$
........................\.........\........\.....\............\projectData\shift_reg.pdb
........................\.........\........\.....\............\shift_reg.log
........................\.........\........\.....\............\shift_reg.pro
........................\.........\........\.....\.imulation\postlayout\shift_reg\verilog.psm
........................\.........\........\.....\..........\..........\.........\_primary.dat
........................\.........\........\.....\..........\..........\.........\_primary.dbs
........................\.........\........\.....\..........\..........\.........\_primary.vhd
........................\.........\........\.....\..........\..........\_info
........................\.........\........\.....\..........\..........\_vmake
........................\.........\hdl\clk_div.v
........................\.........\...\shift_reg.v
........................\.........\shift_reg.prj
........................\.........\.imulation\modelsim.ini
........................\.........\..........\modelsim.log
........................\.........\..........\run.do
........................\.........\..........\vsim.wlf
........................\.........\.martgen\smartgen.aws
........................\.........\.ynthesis\.recordref
........................\.........\.........\backup\shift_reg.srr
........................\.........\.........\run_options.txt
........................\.........\.........\shift_reg.areasrr
........................\.........\.........\shift_reg.edn
........................\.........\.........\shift_reg.map
........................\.........\.........\shift_reg.pdc
........................\.........\.........\shift_reg.sdf
........................\.........\.........\shift_reg.so
........................\.........\.........\shift_reg.srd
........................\.........\.........\shift_reg.srm
........................\.........\.........\shift_reg.srr
........................\.........\.........\shift_reg.srs
........................\.........\.........\shift_reg.szr
........................\.........\.........\shift_reg.tlg
........................\.........\.........\shift_reg_sdc.sdc
........................\.........\.........\shift_reg_syn.prj
........................\.........\.........\stdout.log
........................\.........\.........\.yntmp\shift_reg.plg
........................\.........\.........\traplog.tlg
........................\.........\viewdraw\vf\project.lst
........................\.........\........\viewdraw.ini
........................\移位寄存器.pdf
........................\shift_reg\designer\impl1\simulation\postlayout\shift_reg
........................\.........\........\.....\..........\..........\_temp
........................\.........\........\.....\.hift_reg_fp\projectData
........................\.........\........\.....\.imulation\postlayout
........................\.........\........\.....\shift_reg.dtf
........................\.........\........\.....\shift_reg_fp
........................\.........\........\.....\simulation
........................\.........\........\impl1
........................\.........\synthesis\backup
........................\.........\.........\coreip
........................\.........\.........

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