Description: 1, input signal clk: clock (one for each display pixel clock) reset: reset signal 2, the output signal vga_hs_control: Line sync vga_vs_control: field sync vga_read_dispaly: Red vga_green_dispaly: Green vga_blue_dispaly: Blue 3, technical parameters clk: 24M hs: 30KHZ vs: 57.14HZ
To Search:
File list (Check if you may need any files):
VHDL.docx