Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: freq_divider Download
 Description: 8bit divider, the maximum 256* 2 = 512 min frequency, use emacs to prepare source file, iverilog simulation success
 Downloaders recently: [More information of uploader e1212dison]
 To Search:
File list (Check if you may need any files):
freq_divider
............\freq_divider_8b.v
............\freq_divider_8b.png
............\freq_divider_8b.vcd
............\freq_divider_8b-2.png
............\freq_divider_8b.v~
............\freq_divider_8b.vvp
    

CodeBus www.codebus.net