Description: A clock with the VHDL language program, the software platform is Quartus II 7.2, it is uploaded from the front of the small module combined production, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to get to know and understanding of the VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
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File list (Check if you may need any files):
qq shizhong\cnt24.vhd
...........\cnt60.vhd
...........\db\prev_cmp_shizhong.asm.qmsg
...........\..\prev_cmp_shizhong.fit.qmsg
...........\..\prev_cmp_shizhong.map.qmsg
...........\..\prev_cmp_shizhong.qmsg
...........\..\prev_cmp_shizhong.sim.qmsg
...........\..\prev_cmp_shizhong.tan.qmsg
...........\..\shizhong.asm.qmsg
...........\..\shizhong.asm_labs.ddb
...........\..\shizhong.cbx.xml
...........\..\shizhong.cmp.bpm
...........\..\shizhong.cmp.cdb
...........\..\shizhong.cmp.ecobp
...........\..\shizhong.cmp.hdb
...........\..\shizhong.cmp.logdb
...........\..\shizhong.cmp.rdb
...........\..\shizhong.cmp.tdb
...........\..\shizhong.cmp0.ddb
...........\..\shizhong.cmp_bb.cdb
...........\..\shizhong.cmp_bb.hdb
...........\..\shizhong.cmp_bb.logdb
...........\..\shizhong.cmp_bb.rcf
...........\..\shizhong.dbp
...........\..\shizhong.db_info
...........\..\shizhong.eco.cdb
...........\..\shizhong.eds_overflow
...........\..\shizhong.fit.qmsg
...........\..\shizhong.hier_info
...........\..\shizhong.hif
...........\..\shizhong.map.bpm
...........\..\shizhong.map.cdb
...........\..\shizhong.map.ecobp
...........\..\shizhong.map.hdb
...........\..\shizhong.map.logdb
...........\..\shizhong.map.qmsg
...........\..\shizhong.map_bb.cdb
...........\..\shizhong.map_bb.hdb
...........\..\shizhong.map_bb.logdb
...........\..\shizhong.pre_map.cdb
...........\..\shizhong.pre_map.hdb
...........\..\shizhong.psp
...........\..\shizhong.pss
...........\..\shizhong.rtlv.hdb
...........\..\shizhong.rtlv_sg.cdb
...........\..\shizhong.rtlv_sg_swap.cdb
...........\..\shizhong.sgdiff.cdb
...........\..\shizhong.sgdiff.hdb
...........\..\shizhong.signalprobe.cdb
...........\..\shizhong.sim.cvwf
...........\..\shizhong.sim.hdb
...........\..\shizhong.sim.qmsg
...........\..\shizhong.sim.rdb
...........\..\shizhong.sld_design_entry.sci
...........\..\shizhong.sld_design_entry_dsc.sci
...........\..\shizhong.syn_hier_info
...........\..\shizhong.tan.qmsg
...........\..\shizhong.tis_db_list.ddb
...........\..\wed.wsf
...........\shizhong.asm.rpt
...........\shizhong.bdf
...........\shizhong.done
...........\shizhong.fit.rpt
...........\shizhong.fit.smsg
...........\shizhong.fit.summary
...........\shizhong.flow.rpt
...........\shizhong.map.rpt
...........\shizhong.map.summary
...........\shizhong.pin
...........\shizhong.pof
...........\shizhong.qpf
...........\shizhong.qsf
...........\shizhong.qws
...........\shizhong.sim.rpt
...........\shizhong.sof
...........\shizhong.tan.rpt
...........\shizhong.tan.summary
...........\shizhong.vwf
...........\db
qq shizhong
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