Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: USB2.0 Download
 Description: usb2.0 fpga using vhdl language program quartus environment to achieve
 Downloaders recently: [More information of uploader miyuermi]
 To Search: usb2.0 USB2.0 vhdl fpga quartus USB2.0 FPGA
  • [usb_funct[1].Tar] - usb2.0 IP nuclear, QuartusII or the envi
  • [USB2.0] - usb+ fpga development board schematics,
  • [fifo-1117] - This is the asynchronous FIFO realize th
  • [USB2.0+FPGA+DSP] - usb2.0+ fpga+ dsp development board sche
  • [usb2.0] - USB2.0 paper, use the CY7C68013 chip set
  • [word] - Code was successfully implemented within
  • [USB2.0] - UTMI called USB2.0 Transceiver Macrocell
  • [USB2.0] - usb2.0 specification, programming time t
  • [USB20_FPGA_imagegather] - fpga for usb 2.0 image gather，include so
  • [zx] - CCD color image interpolation algorithm
File list (Check if you may need any files): 
68013_code\68013 slave fifo说明文档.doc
..........\写FIFO\写FIFO\Apptest\ezusbsys.h
..........\......\......\.......\ReadMe.txt
..........\......\......\.......\..lease\StdAfx.obj
..........\......\......\.......\.......\Test.exe
..........\......\......\.......\.......\Test.obj
..........\......\......\.......\.......\Test.res
..........\......\......\.......\.......\TestDlg.obj
..........\......\......\.......\.......\vc60.idb
..........\......\......\.......\Release
..........\......\......\.......\res\cursor1.cur
..........\......\......\.......\...\icon5.ico
..........\......\......\.......\...\Test.ico
..........\......\......\.......\...\Test.rc2
..........\......\......\.......\...\usb.ico
..........\......\......\.......\res
..........\......\......\.......\Resource.h
..........\......\......\.......\StdAfx.cpp
..........\......\......\.......\StdAfx.h
..........\......\......\.......\Test.aps
..........\......\......\.......\Test.clw
..........\......\......\.......\Test.cpp
..........\......\......\.......\Test.dsp
..........\......\......\.......\Test.dsw
..........\......\......\.......\Test.h
..........\......\......\.......\Test.ncb
..........\......\......\.......\Test.opt
..........\......\......\.......\Test.plg
..........\......\......\.......\Test.rc
..........\......\......\.......\TestDlg.cpp
..........\......\......\.......\TestDlg.h
..........\......\......\Apptest
..........\......\......\wr_fifo\cmp_state.ini
..........\......\......\.......\db\cntr_l18.tdf
..........\......\......\.......\..\cntr_n28.tdf
..........\......\......\.......\..\wr_fifo.asm.qmsg
..........\......\......\.......\..\wr_fifo.cbx.xml
..........\......\......\.......\..\wr_fifo.cmp.cdb
..........\......\......\.......\..\wr_fifo.cmp.hdb
..........\......\......\.......\..\wr_fifo.cmp.rdb
..........\......\......\.......\..\wr_fifo.cmp.tdb
..........\......\......\.......\..\wr_fifo.cmp0.ddb
..........\......\......\.......\..\wr_fifo.db_info
..........\......\......\.......\..\wr_fifo.eco.cdb
..........\......\......\.......\..\wr_fifo.fit.qmsg
..........\......\......\.......\..\wr_fifo.hier_info
..........\......\......\.......\..\wr_fifo.hif
..........\......\......\.......\..\wr_fifo.map.cdb
..........\......\......\.......\..\wr_fifo.map.hdb
..........\......\......\.......\..\wr_fifo.map.qmsg
..........\......\......\.......\..\wr_fifo.pre_map.cdb
..........\......\......\.......\..\wr_fifo.pre_map.hdb
..........\......\......\.......\..\wr_fifo.psp
..........\......\......\.......\..\wr_fifo.rtlv.hdb
..........\......\......\.......\..\wr_fifo.rtlv_sg.cdb
..........\......\......\.......\..\wr_fifo.rtlv_sg_swap.cdb
..........\......\......\.......\..\wr_fifo.sgdiff.cdb
..........\......\......\.......\..\wr_fifo.sgdiff.hdb
..........\......\......\.......\..\wr_fifo.signalprobe.cdb
..........\......\......\.......\..\wr_fifo.sld_design_entry.sci
..........\......\......\.......\..\wr_fifo.sld_design_entry_dsc.sci
..........\......\......\.......\..\wr_fifo.smp_dump.txt
..........\......\......\.......\..\wr_fifo.syn_hier_info
..........\......\......\.......\..\wr_fifo.tan.qmsg
..........\......\......\.......\..\wr_fifo_cmp.qrpt
..........\......\......\.......\db
..........\......\......\.......\transcript
..........\......\......\.......\vish_stacktrace.vstf
..........\......\......\.......\vsim.wlf
..........\......\......\.......\work\wr_fifo\verilog.asm
..........\......\......\.......\....\.......\_primary.dat
..........\......\......\.......\....\.......\_primary.vhd
..........\......\......\.......\....\wr_fifo
..........\......\......\.......\....\......._tb\verilog.asm
..........\......\......\.......\....\..........\_primary.dat
..........\......\......\.......\....\..........\_primary.vhd
..........\......\......\.......\....\wr_fifo_tb
..........\......\......\.......\....\_info
..........\......\......\.......\work
..........\......\......\.......\wr_fifo.asm.rpt
..........\......\......\.......\wr_fifo.cdf
..........\......\......\.......\wr_fifo.done
..........\......\......\.......\wr_fifo.fit.eqn

CodeBus www.codebus.net