Welcome!
[Sign In]
!
[Sign Up]
!
Front-page it
|
Collect it
| [
中国-简体中文
]
CodeBus
codebus.net
Hot search:
Source
embeded
web
remote control
p2p
game
More...
FAQ
Fav
Home
SourceCode
Web Code
Develop Tools
Document
E-Books
Other Resource
Get Coins
Member
Location:
Downloads
SourceCode
Embeded-SCM Develop
VHDL-FPGA-Verilog
Title:
ca
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
1kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
bakebear
Description:
Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
Downloaders recently:
[
More information of uploader bakebear
]
To Search:
Verilog GPS
gps vhdl
Verilog receiver
GPS VH
verilog
[
aes_core
] - AES Advanced Encryption Algorithm Verilo
[
IEEE1149JTAG
] - JTAG IEEE 1149 standard, good Dongdong,
[
GPSwsjmscyl
] - Gps detailed pseudo-random code generati
[
c_a
] - GPS in the C/A code generated simple log
[
fft_verilog
] - Verilog hardware description language wi
[
VLSIrfid
] - VLSI implementation of RFID
[
code_gen_rtl
] - GPS/GLONASS PRN code generator. VHDL sou
[
fft2
] - 512 points, eight base 2fft program. Bas
[
CAcode
] - CA Code of FPGA implementation, verilog
[
HAS160
] - HAS-160 Cipher algorithm verilog code
File list
(Check if you may need any files):
ca\ca1.v ..\LFSR_10bits11.v ..\LFSR_10bits21.v ca
Main Category
SourceCode
Web Code
Develop Tools
Document
Other resource
Category
About site
Total codes:
120
M
Total size:
1500
GB
Today updated:368
Members:1688565
Today members:634
Total members:198568
Downloaded:1200M
Sign UP
Help
Support
What's CodeBus
SiteMap
Contact us
CodeBus www.codebus.net
“CodeBus” is the largest source code store in internet!
1999-2018
CodeBus
All Rights Reserved.