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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: spimaster Download
 Description: SPI IP core supporting SD/MMC
 Downloaders recently: [More information of uploader zhang_longhai]
File list (Check if you may need any files):
spimaster
.........\Aldec
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\design0
.........\.....\.......\compile
.........\.....\.......\.......\CVS
.........\.....\.......\.......\...\Entries
.........\.....\.......\.......\...\Repository
.........\.....\.......\.......\...\Root
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\design0.adf
.........\.....\.......\fsm.set
.........\.....\.......\log
.........\.....\.......\...\CVS
.........\.....\.......\...\...\Entries
.........\.....\.......\...\...\Repository
.........\.....\.......\...\...\Root
.........\.....\.......\src
.........\.....\.......\...\CVS
.........\.....\.......\...\...\Entries
.........\.....\.......\...\...\Repository
.........\.....\.......\...\...\Root
.........\.....\.......\...\initSD.asf
.........\.....\.......\...\readWriteSDBlock.asf
.........\.....\.......\...\readWriteSPIWireData.asf
.........\.....\.......\...\sendCmd.asf
.........\.....\.......\...\spiCtrl.asf
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\testCase0.v
.........\.....\testHarness.v
.........\CVS
.........\...\Entries
.........\...\Repository
.........\...\Root
.........\doc
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\spiMaster_FSM.pdf
.........\...\spiMaster_Specification.pdf
.........\...\src
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\...\spiMaster_Specification.sxw
.........\model
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\sdModel.v
.........\.....\wb_master_model.v
.........\RTL
.........\...\ctrlStsRegBI.v
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\initSD.v
.........\...\readWriteSDBlock.v
.........\...\readWriteSPIWireData.v
.........\...\sendCmd.v
.........\...\sm_dpMem_dc.v
.........\...\sm_fifoRTL.v
.........\...\sm_RxFifo.v
.........\...\sm_RxFifoBI.v
.........\...\sm_TxFifo.v
.........\...\sm_TxFifoBI.v
.........\...\spiCtrl.v
.........\...\spiMaster.v
.........\...\spiMasterWishBoneBI.v
.........\...\spiMaster_defines.v
.........\...\spiTxRxData.v
.........\...\timescale.v
.........\sim
.........\...\build_icarus.bat
.........\...\compile.do
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\filelist.icarus
.........\...\modelsim.ini
.........\...\run.do
.........\...\run_icarus.bat
.........\...\wave.do
.........\syn
.........\...\CVS
    

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