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Title: clk_en_gen Download
 Description: Reliable clock generator, using synchronous design, compiled simulation, the results of the correct
 Downloaders recently: [More information of uploader yjh841117]
File list (Check if you may need any files):
clk_en_gen
..........\clk_en_gen.asm.rpt
..........\clk_en_gen.done
..........\clk_en_gen.eda.rpt
..........\clk_en_gen.fit.rpt
..........\clk_en_gen.fit.smsg
..........\clk_en_gen.fit.summary
..........\clk_en_gen.flow.rpt
..........\clk_en_gen.map.rpt
..........\clk_en_gen.map.summary
..........\clk_en_gen.pin
..........\clk_en_gen.pof
..........\clk_en_gen.qpf
..........\clk_en_gen.qsf
..........\clk_en_gen.qws
..........\clk_en_gen.sim.rpt
..........\clk_en_gen.sof
..........\clk_en_gen.tan.rpt
..........\clk_en_gen.tan.summary
..........\clk_en_gen.v
..........\clk_en_gen.vwf
..........\db
..........\..\add_sub_2rh.tdf
..........\..\clk_en_gen.asm.qmsg
..........\..\clk_en_gen.cbx.xml
..........\..\clk_en_gen.cmp.bpm
..........\..\clk_en_gen.cmp.cdb
..........\..\clk_en_gen.cmp.ecobp
..........\..\clk_en_gen.cmp.hdb
..........\..\clk_en_gen.cmp.logdb
..........\..\clk_en_gen.cmp.rdb
..........\..\clk_en_gen.cmp.tdb
..........\..\clk_en_gen.cmp0.ddb
..........\..\clk_en_gen.cmp_bb.cdb
..........\..\clk_en_gen.cmp_bb.hdb
..........\..\clk_en_gen.cmp_bb.logdb
..........\..\clk_en_gen.cmp_bb.rcf
..........\..\clk_en_gen.dbp
..........\..\clk_en_gen.db_info
..........\..\clk_en_gen.eco.cdb
..........\..\clk_en_gen.eda.qmsg
..........\..\clk_en_gen.eds_overflow
..........\..\clk_en_gen.fit.qmsg
..........\..\clk_en_gen.fnsim.cdb
..........\..\clk_en_gen.fnsim.hdb
..........\..\clk_en_gen.fnsim.qmsg
..........\..\clk_en_gen.hier_info
..........\..\clk_en_gen.hif
..........\..\clk_en_gen.map.bpm
..........\..\clk_en_gen.map.cdb
..........\..\clk_en_gen.map.ecobp
..........\..\clk_en_gen.map.hdb
..........\..\clk_en_gen.map.logdb
..........\..\clk_en_gen.map.qmsg
..........\..\clk_en_gen.map_bb.cdb
..........\..\clk_en_gen.map_bb.hdb
..........\..\clk_en_gen.map_bb.logdb
..........\..\clk_en_gen.pre_map.cdb
..........\..\clk_en_gen.pre_map.hdb
..........\..\clk_en_gen.psp
..........\..\clk_en_gen.pss
..........\..\clk_en_gen.rpp.qmsg
..........\..\clk_en_gen.rtlv.hdb
..........\..\clk_en_gen.rtlv_sg.cdb
..........\..\clk_en_gen.rtlv_sg_swap.cdb
..........\..\clk_en_gen.sgate.rvd
..........\..\clk_en_gen.sgate_sm.rvd
..........\..\clk_en_gen.sgdiff.cdb
..........\..\clk_en_gen.sgdiff.hdb
..........\..\clk_en_gen.signalprobe.cdb
..........\..\clk_en_gen.sim.cvwf
..........\..\clk_en_gen.sim.hdb
..........\..\clk_en_gen.sim.qmsg
..........\..\clk_en_gen.sim.rdb
..........\..\clk_en_gen.sld_design_entry.sci
..........\..\clk_en_gen.sld_design_entry_dsc.sci
..........\..\clk_en_gen.syn_hier_info
..........\..\clk_en_gen.tan.qmsg
..........\..\clk_en_gen.tis_db_list.ddb
..........\..\prev_cmp_clk_en_gen.asm.qmsg
..........\..\prev_cmp_clk_en_gen.eda.qmsg
..........\..\prev_cmp_clk_en_gen.fit.qmsg
..........\..\prev_cmp_clk_en_gen.map.qmsg
..........\..\prev_cmp_clk_en_gen.qmsg
..........\..\prev_cmp_clk_en_gen.tan.qmsg
..........\..\wed.wsf
..........\simulation
..........\..........\modelsim
..........\..........\........\clk_en_gen.vo
..........\..........\........\clk_en_gen_modelsim.xrf
..........\..........\........\clk_en_gen_v.sdo
    

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