Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: verilogHDL Download
 Description: Finite state machine (request, quot Threequot) approach to design a client with Asynchronous Clear reversible synchronous counter module 6. At the same time providing a single digital control and digital display shows the status of the two 3LED displayed.
 Downloaders recently: [More information of uploader yun_sui]
 To Search:
  • [statemachinedesign.Rar] - detailed state machine design, VHDL, is
  • [fsm] - Detection of input data of
  • [work2CNT10] - Clear design with asynchronous and synch
  • [VHDL_counter] - This is an increase or decrease in use o
  • [FSM] - FSM archive contains three stages of wri
File list (Check if you may need any files):
有限状态机实现可逆模六计数器
............................\Verilog  HDL语言.txt
............................\工程文件_project_ok
............................\...................\db
............................\...................\..\ok.asm.qmsg
............................\...................\..\ok.asm_labs.ddb
............................\...................\..\ok.cbx.xml
............................\...................\..\ok.cmp.bpm
............................\...................\..\ok.cmp.cdb
............................\...................\..\ok.cmp.ecobp
............................\...................\..\ok.cmp.hdb
............................\...................\..\ok.cmp.kpt
............................\...................\..\ok.cmp.logdb
............................\...................\..\ok.cmp.rdb
............................\...................\..\ok.cmp.tdb
............................\...................\..\ok.cmp0.ddb
............................\...................\..\ok.cmp_merge.kpt
............................\...................\..\ok.db_info
............................\...................\..\ok.eco.cdb
............................\...................\..\ok.eds_overflow
............................\...................\..\ok.fit.qmsg
............................\...................\..\ok.fnsim.hdb
............................\...................\..\ok.fnsim.qmsg
............................\...................\..\ok.hier_info
............................\...................\..\ok.hif
............................\...................\..\ok.map.bpm
............................\...................\..\ok.map.cdb
............................\...................\..\ok.map.ecobp
............................\...................\..\ok.map.hdb
............................\...................\..\ok.map.kpt
............................\...................\..\ok.map.logdb
............................\...................\..\ok.map.qmsg
............................\...................\..\ok.map_bb.cdb
............................\...................\..\ok.map_bb.hdb
............................\...................\..\ok.map_bb.hdbx
............................\...................\..\ok.map_bb.logdb
............................\...................\..\ok.pre_map.cdb
............................\...................\..\ok.pre_map.hdb
............................\...................\..\ok.psp
............................\...................\..\ok.rpp.qmsg
............................\...................\..\ok.rtlv.hdb
............................\...................\..\ok.rtlv_sg.cdb
............................\...................\..\ok.rtlv_sg_swap.cdb
............................\...................\..\ok.sgate.rvd
............................\...................\..\ok.sgate_sm.rvd
............................\...................\..\ok.sgdiff.cdb
............................\...................\..\ok.sgdiff.hdb
............................\...................\..\ok.sim.cvwf
............................\...................\..\ok.sim.hdb
............................\...................\..\ok.sim.qmsg
............................\...................\..\ok.sim.rdb
............................\...................\..\ok.simfam
............................\...................\..\ok.sld_design_entry.sci
............................\...................\..\ok.sld_design_entry_dsc.sci
............................\...................\..\ok.smp_dump.txt
............................\...................\..\ok.syn_hier_info
............................\...................\..\ok.tan.qmsg
............................\...................\..\ok.tis_db_list.ddb
............................\...................\..\ok.tmw_info
............................\...................\..\prev_cmp_ok.asm.qmsg
............................\...................\..\prev_cmp_ok.fit.qmsg
............................\...................\..\prev_cmp_ok.map.qmsg
............................\...................\..\prev_cmp_ok.qmsg
............................\....

CodeBus www.codebus.net