Description: Based on VHDL (verilog) Language Design and Implementation of UART. UART fully mimic the function of AVR, and AVR debugging interface directly to achieve. Overall integrity of the information.
To Search:
- [AVR_Core] - Synthesizable model of Atmel Application
File list (Check if you may need any files):
fpga
....\V0p10
....\.....\db
....\.....\src
....\.....\...\divider.v
....\.....\...\ebi.v
....\.....\...\rxd.v
....\.....\...\top.v
....\.....\...\txd.v
....\.....\...\uart.v
....\.....\testbench
....\.....\.........\cycloneII_v
....\.....\.........\...........\_info
....\.....\.........\tcl_stacktrace.txt
....\.....\.........\top_tb.v
....\.....\.........\transcript
....\.....\.........\uart.cr.mti
....\.....\.........\uart.mpf
....\.....\.........\vish_stacktrace.vstf
....\.....\.........\vsim.wlf
....\.....\.........\vsim_stacktrace.vstf
....\.....\.........\work
....\.....\.........\....\divider
....\.....\.........\....\.......\verilog.asm
....\.....\.........\....\.......\_primary.dat
....\.....\.........\....\.......\_primary.vhd
....\.....\.........\....\division
....\.....\.........\....\........\verilog.asm
....\.....\.........\....\........\_primary.dat
....\.....\.........\....\........\_primary.vhd
....\.....\.........\....\ebi
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\_primary.vhd
....\.....\.........\....\rxd
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\_primary.vhd
....\.....\.........\....\top
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\_primary.vhd
....\.....\.........\....\top_tb
....\.....\.........\....\......\verilog.asm
....\.....\.........\....\......\_primary.dat
....\.....\.........\....\......\_primary.vhd
....\.....\.........\....\txd
....\.....\.........\....\...\verilog.asm
....\.....\.........\....\...\_primary.dat
....\.....\.........\....\...\_primary.vhd
....\.....\.........\....\uart
....\.....\.........\....\....\verilog.asm
....\.....\.........\....\....\_primary.dat
....\.....\.........\....\....\_primary.vhd
....\.....\.........\....\_info
....\.....\.........\....\_temp
....\.....\top.bsf
....\.....\uart.asm.rpt
....\.....\uart.cdf
....\.....\uart.done
....\.....\uart.dpf
....\.....\uart.fit.rpt
....\.....\uart.fit.smsg
....\.....\uart.fit.summary
....\.....\uart.flow.rpt
....\.....\uart.map.rpt
....\.....\uart.map.smsg
....\.....\uart.map.summary
....\.....\uart.pin
....\.....\uart.pof
....\.....\uart.qpf
....\.....\uart.qsf
....\.....\uart.qws
....\.....\uart.sof
....\.....\uart.tan.rpt
....\.....\uart.tan.summary
....\.....\uart_description.txt
Mcu
...\UartTest
...\........\Debug
...\........\.....\Exe
...\........\.....\List
...\........\.....\Obj
...\........\FpgaInc.h
...\........\main.c
...\........\settings
...\........\........\test.cspy.bat
...\........\........\test.dbgdt
...\........\........\test.dni
...\........\........\test.wsdt
...\........\........\UartTest.cspy.bat
...\........\........\UartTest.dni
...\........\........\UartTest.wsdt
...\........\stdinc.h
...\........\UartCtrl.c
...\........\UartCtrl.h
...\........\UartTest.dep
...\........\UartTest.ewd
...\........\UartTest.ewp
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