Description: FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
- [fdividing] - floating-point division subroutine, high
- [divider] - Introduced the divider design, using ver
- [div2] - 32 divider dividend and divisor are 16-b
- [divide] - Divider design used in this paper, the p
- [32divider] - 32-bit binary divider 2
- [divide] - Divider
- [LCD] - LCD1602-driven FPGA-based, verilog code
- [gaojindukuaisuchufa] - High-precision floating-point division o
- [chufaqiziliao] - Divider information, so the divider indi
- [fpuvhdl_latest.tar] - FPGA realization of floating-point opera
File list (Check if you may need any files):
新建 Microsoft Word 文档.doc