Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: 1 Download
 Description: The realization of the clock function, count, reset, adjust the time, both function-plus-one seconds, add the button functions.
 Downloaders recently: [More information of uploader 465580241]
 To Search:
  • [Reset] - A software reset on the papers, this art
File list (Check if you may need any files):
1.txt
    

CodeBus www.codebus.net