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- 2012-11-26
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Description: ENTITY uart IS
PORT ( SIGNAL clock,reset : IN STD_LOGIC
SIGNAL sdatain : IN STD_LOGIC
SIGNAL oready, sdataout : INOUT STD_LOGIC
SIGNAL iready : INOUT STD_LOGIC
SIGNAL charin : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
SIGNAL charout : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
SIGNAL write, read : INOUT STD_LOGIC
SIGNAL sdatain_out : OUT STD_LOGIC
SIGNAL sdataout_out : OUT STD_LOGIC
SIGNAL reset_out : OUT STD_LOGIC
SIGNAL sample_clock_out : OUT STD_LOGIC )
END uart
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audio_init.vhd
audio_interface.vhd
audio_loopback.vhd
audio_serial_io.vhd
top_level.vhd
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