viterbidecoder viterbi decoder implementation by v - CodeBus

Welcome！[Sign In] ！[Sign Up]！

Front-page it | Collect it | [中国-简体中文]

FAQ Fav

Location:

Embeded-SCM Develop

VHDL-FPGA-Verilog

Title: viterbidecoder

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
5kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
zhou_li_keda

Description: viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code

Downloaders recently: [More information of uploader zhou_li_keda]

To Search: viterbi decoder verilog viterbi verilog viterbi viterbidecoder in verilog verilog code of viterbi decoder

[ConvolutionalencodingandViterbidecodingwith] - convolutional coding and Viterbi decodin
[Viterbidecoder] - Viterbi decoder low power design Verilog
[viterbi_decoder_sources_code_verilog] - Viterbi decoder, use verilog HDL languag
[conv_enc] - This is a VERILOG HDL with the preparati
[viterbi] - This is a language VERILOG HDL by the vi
[conv_vhdl] - Verilog implementation using convolution

File list (Check if you may need any files):

viterbidecoder
..............\ASC.v
..............\BMU.v
..............\opt.v
..............\shiftReg.v
..............\top.v

CodeBus www.codebus.net

“CodeBus” is the largest source code store in internet!

1999-2018 CodeBus All Rights Reserved.