Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: dianzibiao Download
 Description: To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2
 Downloaders recently: [More information of uploader 364388520]
 To Search:
File list (Check if you may need any files):
简单电子表
..........\chuan.done
..........\chuan.dpf
..........\chuan.flow.rpt
..........\chuan.map.rpt
..........\chuan.map.summary
..........\CHUAN.qpf
..........\chuan.qsf
..........\CHUAN.qws
..........\CHUAN.VHD
..........\db
..........\..\chuan.cbx.xml
..........\..\chuan.cmp.rdb
..........\..\chuan.dbp
..........\..\chuan.db_info
..........\..\chuan.eco.cdb
..........\..\chuan.hier_info
..........\..\chuan.hif
..........\..\chuan.map.bpm
..........\..\chuan.map.cdb
..........\..\chuan.map.ecobp
..........\..\chuan.map.hdb
..........\..\chuan.map.logdb
..........\..\chuan.map.qmsg
..........\..\chuan.map_bb.cdb
..........\..\chuan.map_bb.hdb
..........\..\chuan.map_bb.logdb
..........\..\chuan.pre_map.cdb
..........\..\chuan.pre_map.hdb
..........\..\chuan.psp
..........\..\chuan.pss
..........\..\chuan.rtlv.hdb
..........\..\chuan.rtlv_sg.cdb
..........\..\chuan.rtlv_sg_swap.cdb
..........\..\chuan.sgdiff.cdb
..........\..\chuan.sgdiff.hdb
..........\..\chuan.sld_design_entry.sci
..........\..\chuan.sld_design_entry_dsc.sci
..........\..\chuan.syn_hier_info
..........\..\chuan.tis_db_list.ddb
..........\..\prev_cmp_chuan.map.qmsg
..........\..\prev_cmp_CHUAN.qmsg
    

CodeBus www.codebus.net