Description: DIP switch to an analog signal PWM switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
- [PWM] - Pulse width modulation, VHDL coding, inc
File list (Check if you may need any files):
PWMtest
.......\cmp_state.ini
.......\db
.......\..\pwmtest.asm.qmsg
.......\..\pwmtest.cbx.xml
.......\..\pwmtest.cmp.cdb
.......\..\pwmtest.cmp.hdb
.......\..\pwmtest.cmp.rdb
.......\..\pwmtest.cmp.tdb
.......\..\pwmtest.cmp0.ddb
.......\..\pwmtest.db_info
.......\..\pwmtest.eco.cdb
.......\..\pwmtest.fit.qmsg
.......\..\pwmtest.hier_info
.......\..\pwmtest.hif
.......\..\pwmtest.map.cdb
.......\..\pwmtest.map.hdb
.......\..\pwmtest.map.qmsg
.......\..\pwmtest.pre_map.cdb
.......\..\pwmtest.pre_map.hdb
.......\..\pwmtest.psp
.......\..\pwmtest.rtlv.hdb
.......\..\pwmtest.rtlv_sg.cdb
.......\..\pwmtest.rtlv_sg_swap.cdb
.......\..\pwmtest.sgdiff.cdb
.......\..\pwmtest.sgdiff.hdb
.......\..\pwmtest.sld_design_entry.sci
.......\..\pwmtest.sld_design_entry_dsc.sci
.......\..\pwmtest.syn_hier_info
.......\..\pwmtest.tan.qmsg
.......\..\pwmtest_cmp.qrpt
.......\pwmtest.asm.rpt
.......\pwmtest.cdf
.......\pwmtest.done
.......\pwmtest.fit.eqn
.......\pwmtest.fit.rpt
.......\pwmtest.fit.summary
.......\pwmtest.flow.rpt
.......\pwmtest.map.eqn
.......\pwmtest.map.rpt
.......\pwmtest.map.summary
.......\pwmtest.pin
.......\pwmtest.pof
.......\pwmtest.qpf
.......\pwmtest.qsf
.......\pwmtest.qws
.......\pwmtest.tan.rpt
.......\pwmtest.tan.summary
.......\pwmtest.v
.......\pwm_fpga.vhdl
Download