ctrller This code is to control the SDRAM of the V

Title: ctrller

Category:
VHDL-FPGA-Verilog
Tags:
File Size:
9kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
bradley0226

Description: This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to call the module

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