fpga_drive_ad7892 The use of FPGA-driven 12-bit AD

Title: fpga_drive_ad7892

Category:
SCM
Tags:
File Size:
493kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
weiyong321

Description: The use of FPGA-driven 12-bit AD7892 analog to digital conversion, and data is stored in the SRAM. FPGA model EP1C3-144. Through the LED will be 12-bit AD value is displayed.

Downloaders recently: [More information of uploader weiyong321]

To Search: fpga ad7892 vh

[ad_7266_32_v1_00_a] - The Verilog driver of AD7266 has been si
[AD7708code] - High-precision 16-bit AD converter AD770
[FPGAAD] - FPGA control AD procedure
[ad7862] - Upper and lower drive to achieve communi
[ads7822] - it is convinient for us to use A/D conve
[(FPGA)] - DAC0832 on the oscilloscope display circ
[Altera_timing] - This document describes Altera' s FPG
[tlc3548VHDL] - VHDL COUNTER TLC3548
[RS-decode_base-on-FPGA] - This is a wonderful master rs decode the
[FPGA] - FPGA

File list (Check if you may need any files):

fpga_drive_ad7892
.................\ad_control.bsf
.................\ad_control.vhd
.................\db
.................\..\fpga_and_ad.db_info
.................\..\fpga_and_ad.eco.cdb
.................\..\fpga_and_ad.sld_design_entry.sci
.................\fpga_and_ad.asm.rpt
.................\fpga_and_ad.bdf
.................\fpga_and_ad.cdf
.................\fpga_and_ad.done
.................\fpga_and_ad.dpf
.................\fpga_and_ad.fit.rpt
.................\fpga_and_ad.fit.smsg
.................\fpga_and_ad.fit.summary
.................\fpga_and_ad.flow.rpt
.................\fpga_and_ad.map.rpt
.................\fpga_and_ad.map.summary
.................\fpga_and_ad.pin
.................\fpga_and_ad.pof
.................\fpga_and_ad.qpf
.................\fpga_and_ad.qsf
.................\fpga_and_ad.qws
.................\fpga_and_ad.sof
.................\fpga_and_ad.tan.rpt
.................\fpga_and_ad.tan.summary
.................\fpga_and_ad_assignment_defaults.qdf
.................\FPGA_AND_USB_080507修改
.................\.......................\bianliang.vhd
.................\.......................\count.vwf
.................\.......................\Data_to_Usb.bsf
.................\.......................\Data_to_Usb.vhd
.................\.......................\db
.................\.......................\..\FPGA_AND_USB.asm.qmsg
.................\.......................\..\FPGA_AND_USB.cbx.xml
.................\.......................\..\FPGA_AND_USB.cmp.cdb
.................\.......................\..\FPGA_AND_USB.cmp.hdb
.................\.......................\..\FPGA_AND_USB.cmp.kpt
.................\.......................\..\FPGA_AND_USB.cmp.logdb
.................\.......................\..\FPGA_AND_USB.cmp.rdb
.................\.......................\..\FPGA_AND_USB.cmp.tdb
.................\.......................\..\FPGA_AND_USB.cmp0.ddb
.................\.......................\..\FPGA_AND_USB.dbp
.................\.......................\..\FPGA_AND_USB.db_info
.................\.......................\..\FPGA_AND_USB.eco.cdb
.................\.......................\..\FPGA_AND_USB.eds_overflow
.................\.......................\..\FPGA_AND_USB.fit.qmsg
.................\.......................\..\FPGA_AND_USB.hier_info
.................\.......................\..\FPGA_AND_USB.hif
.................\.......................\..\FPGA_AND_USB.map.cdb
.................\.......................\..\FPGA_AND_USB.map.hdb
.................\.......................\..\FPGA_AND_USB.map.logdb
.................\.......................\..\FPGA_AND_USB.map.qmsg
.................\.......................\..\FPGA_AND_USB.pre_map.cdb
.................\.......................\..\FPGA_AND_USB.pre_map.hdb
.................\.......................\..\FPGA_AND_USB.psp
.................\.......................\..\FPGA_AND_USB.rtlv.hdb
.................\.......................\..\FPGA_AND_USB.rtlv_sg.cdb
.................\.......................\..\FPGA_AND_USB.rtlv_sg_swap.cdb
.................\.......................\..\FPGA_AND_USB.sgdiff.cdb
.................\.......................\..\FPGA_AND_USB.sgdiff.hdb
.................\.......................\..\FPGA_AND_USB.signalprobe.cdb
.................\.......................\..\FPGA_AND_USB.sim.hdb
.................\.......................\..\FPGA_AND_USB.sim.qmsg
.................\.......................\..\FPGA_AND_USB.sim.rdb
.................\.......................\..\FPGA_AND_USB.sim.vwf
.................\.......................\..\FPGA_AND_USB.sld_design_entry.sci
.................\.......................\..\FPGA_AND_USB.sld_design_entry_dsc.sci
.................\.......................\..\FPGA_AND_USB.syn_hier_info
.................\.......................\..\FPGA_AND_USB.tan.qmsg
.................\.......................\..\wed.zsf
.................\.......................\depthcount.bsf
.................\.......................\depthcount.vhd
.................\.......................\Depth_direction.vhd
.................\.......................\dep

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net