TestBench 、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (

Title: TestBench

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VHDL-FPGA-Verilog
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2012-11-26
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jialeixiaoxin

Description: 、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_logic_vector(v_remd,DWIDTH)) report "ERROR in division!" severity failure

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