Description: //Receiver decoder module (which can be integrated)// at the beginning of the signal received by the sending end to send a signal 10,// that is, 10+ M sequence, so we at the beginning of each receive a signal for a cumulative computing// When the peak is reached when that synchronization, access to the process of synchronous demodulation (mainbody).// That is, a signal from each corresponding to the sum of the multiplication,// in the solution of 31 receive a signal after the judge, that the receiver is greater than 0 to 1, less than 0 that received 0.
To Search:
- [M_generate] - m sequence code generated, vhdl hardware
- [m] - M series source code for the base-band s
- [m] - m sequence signal generator designed for
File list (Check if you may need any files):
decode.v
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