Description: Prepared using verilog HDL and string conversion module, in the ISE software simulation, and can also be integrated
To Search:
- [s_pandp_s] - prepared using VHDL and string conversio
- [S2P_xapp194] - VHDL, verilog Series and conversion comp
- [p2s16_1] - Some time ago to see someone in the onli
- [bc_6] - To implement the six-bit data width and
- [config_dac] - Verilog realize spi interface FPGA to ac
- [p2s] - And series converter: the input signal i
- [verilog] - Example Collection contains verilog lang
- [s2p] - A string and convert the Verilog source
- [signal_output] - The document may download to FPGA chip t
File list (Check if you may need any files):
chuan2
......\.lso
......\1_bencher.prj
......\chuan2.ise
......\chuan2.ntrc_log
......\chuan2.restore
......\chuan2_xdb
......\..........\cst.xbcd
......\..........\tmp
......\..........\...\ise
......\..........\...\...\version
......\..........\...\...\__OBJSTORE__
......\..........\...\...\............\Autonym
......\..........\...\...\............\common
......\..........\...\...\............\HierarchicalDesign
......\..........\...\...\............\..................\HDProject
......\..........\...\...\............\..................\.........\HDProject
......\..........\...\...\............\..................\.........\HDProject_StrTbl
......\..........\...\...\............\..................\__stored_object_table__
......\..........\...\...\............\ISimPlugin
......\..........\...\...\............\..........\SignalOrdering1
......\..........\...\...\............\..........\...............\testt_isim_beh.exe
......\..........\...\...\............\..........\...............\testt_isim_beh.exe_StrTbl
......\..........\...\...\............\..........\...............\test_isim_beh.exe
......\..........\...\...\............\..........\...............\test_isim_beh.exe_StrTbl
......\..........\...\...\............\PnAutoRun
......\..........\...\...\............\.........\Scripts
......\..........\...\...\............\.........\.......\RunOnce_tcl
......\..........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
......\..........\...\...\............\ProjectNavigator
......\..........\...\...\............\................\dpm_project_main
......\..........\...\...\............\................\................\dpm_project_main
......\..........\...\...\............\................\................\dpm_project_main_StrTbl
......\..........\...\...\............\................\................\NameMap
......\..........\...\...\............\................\................\NameMap_StrTbl
......\..........\...\...\............\................\__stored_objects__
......\..........\...\...\............\................\__stored_objects___StrTbl
......\..........\...\...\............\................\__stored_object_table__
......\..........\...\...\............\ProjectNavigatorGui
......\..........\...\...\............\...................\GuiProjectData
......\..........\...\...\............\...................\GuiProjectData_StrTbl
......\..........\...\...\............\SrcCtrl
......\..........\...\...\............\.......\SavedOptions
......\..........\...\...\............\STE
......\..........\...\...\............\xreport
......\..........\...\...\............\.......\Gc_RvReportViewer-Current-Module
......\..........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
......\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-converter
......\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-converter_StrTbl
......\..........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
......\..........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
......\..........\...\...\............\_ProjRepoInternal_
......\..........\...\...\__REGISTRY__
......\..........\...\...\............\Autonym
......\..........\...\...\............\.......\regkeys
......\..........\...\...\............\bitgen
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\common
......\..........\...\...\............\......\regkeys
......\..........\...\...\............\cpldfit
......\..........\...\...\............\.......\regkeys
......\..........\...\...\............\Cs
......\..........\...\...\............\..\regkeys
......\..........\...\...\............\dumpngdio
......\..........\...\...\............\.........\regkeys
......\..........\...\...\............\fuse
......\..........\...\...\............\....\regkeys
......\..........\...\...\............\HierarchicalDesign
......\..........\...\...\............\..................\HDProject
......\..........\...\...\............\............
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