Description: Verilog bus I2c realized, can be used to design quartus
- [IIC] - Standard 80C51 single-chip simulation of
- [I2Cslave1] - I2C slave for FPGA and CPLD.
- [i2c] - Verilog source I2C protocol, including t
- [i2c] - This is an IIC interface procedures for
- [i2c_ip] - I2C' s ip nuclear, Verilog realizatio
- [I2C] - Verilog code for IIC
- [altera_avalon_i2c_V90] - I2C IP for Quartus V9.0, can used in SOP
- [i2cslave_latest.tar] - hi this is i2c master in verilog
File list (Check if you may need any files):
i2c_slv_ctrl.v