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Title: sclock Download
 Description: FPGA EP2C5Q288C8 the original serial code, test that is used to open OK.
 Downloaders recently: [More information of uploader pschen083]
 To Search: fpga
  • [serial_VHDL] - FPGA for serial communication procedure
  • [Altera-FPGA-Guide] - Altera FPGA development tools detailed g
  • [FIFO] - Asynchronous FIFO verilog realize realiz
  • [cyclic] - FPGA serial communication program, accep
  • [UART] - Input clock 20M, the baud rate for 9600,
  • [gh_uart_16550_080407] - Commonly used in FPGA development serial
  • [Serial] - FPGA and the PC serial communication pro
  • [Fifo] - A FIFO source code, based on Altera FPGA
  • [FPGAuartdebug] - FPGA serial debugger interface, using VH
File list (Check if you may need any files):
sclock
......\counter.bsf
......\counter.v
......\counter.v.bak
......\db
......\..\add_sub_lkc.tdf
......\..\add_sub_mkc.tdf
......\..\alt_u_div_gve.tdf
......\..\alt_u_div_kve.tdf
......\..\lpm_divide_05m.tdf
......\..\lpm_divide_25m.tdf
......\..\lpm_divide_tcm.tdf
......\..\lpm_divide_vcm.tdf
......\..\prev_cmp_sclock.asm.qmsg
......\..\prev_cmp_sclock.fit.qmsg
......\..\prev_cmp_sclock.map.qmsg
......\..\prev_cmp_sclock.qmsg
......\..\prev_cmp_sclock.sim.qmsg
......\..\prev_cmp_sclock.tan.qmsg
......\..\sclock.asm.qmsg
......\..\sclock.asm_labs.ddb
......\..\sclock.cbx.xml
......\..\sclock.cmp.bpm
......\..\sclock.cmp.cdb
......\..\sclock.cmp.ecobp
......\..\sclock.cmp.hdb
......\..\sclock.cmp.logdb
......\..\sclock.cmp.rdb
......\..\sclock.cmp.tdb
......\..\sclock.cmp0.ddb
......\..\sclock.cmp2.ddb
......\..\sclock.cmp_bb.cdb
......\..\sclock.cmp_bb.hdb
......\..\sclock.cmp_bb.logdb
......\..\sclock.cmp_bb.rcf
......\..\sclock.dbp
......\..\sclock.db_info
......\..\sclock.eco.cdb
......\..\sclock.fit.qmsg
......\..\sclock.hier_info
......\..\sclock.hif
......\..\sclock.map.bpm
......\..\sclock.map.cdb
......\..\sclock.map.ecobp
......\..\sclock.map.hdb
......\..\sclock.map.logdb
......\..\sclock.map.qmsg
......\..\sclock.map_bb.cdb
......\..\sclock.map_bb.hdb
......\..\sclock.map_bb.logdb
......\..\sclock.pre_map.cdb
......\..\sclock.pre_map.hdb
......\..\sclock.psp
......\..\sclock.pss
......\..\sclock.rtlv.hdb
......\..\sclock.rtlv_sg.cdb
......\..\sclock.rtlv_sg_swap.cdb
......\..\sclock.sgdiff.cdb
......\..\sclock.sgdiff.hdb
......\..\sclock.signalprobe.cdb
......\..\sclock.sim_ori.vwf
......\..\sclock.sld_design_entry.sci
......\..\sclock.sld_design_entry_dsc.sci
......\..\sclock.syn_hier_info
......\..\sclock.tan.qmsg
......\..\sclock.tis_db_list.ddb
......\..\sign_div_unsign_7kh.tdf
......\..\sign_div_unsign_9kh.tdf
......\..\wed.wsf
......\div.bsf
......\div.v
......\sclock.asm.rpt
......\sclock.bdf
......\sclock.cdf
......\sclock.done
......\sclock.fit.rpt
......\sclock.fit.smsg
......\sclock.fit.summary
......\sclock.flow.rpt
......\sclock.map.rpt
......\sclock.map.smsg
......\sclock.map.summary
......\sclock.pin
......\sclock.pof
......\sclock.qpf
......\sclock.qsf
......\sclock.qws
......\sclock.sim.rpt
......\sclock.sof
......\sclock.tan.rpt
......\sclock.tan.summary
......\sclock.vwf
......\segmain.bsf
......\segmain.v
......\setup.tcl
......\setup.tcl.bak
    

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