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Title: SIN Download
 Description: The use of VHDL language and CPLD chip 39KHz signal generated
 Downloaders recently: [More information of uploader zhuyingbo2005]
 To Search: sin sin vhdl sin vhdl
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File list (Check if you may need any files):
SIN
...\db
...\..\prev_cmp_SIN.asm.qmsg
...\..\prev_cmp_SIN.fit.qmsg
...\..\prev_cmp_SIN.map.qmsg
...\..\prev_cmp_SIN.qmsg
...\..\prev_cmp_SIN.tan.qmsg
...\..\SIN.asm.qmsg
...\..\SIN.asm_labs.ddb
...\..\SIN.cbx.xml
...\..\SIN.cmp.cdb
...\..\SIN.cmp.hdb
...\..\SIN.cmp.logdb
...\..\SIN.cmp.rdb
...\..\SIN.cmp.tdb
...\..\SIN.cmp0.ddb
...\..\SIN.dbp
...\..\SIN.db_info
...\..\SIN.eco.cdb
...\..\SIN.fit.qmsg
...\..\SIN.hier_info
...\..\SIN.hif
...\..\SIN.map.cdb
...\..\SIN.map.hdb
...\..\SIN.map.logdb
...\..\SIN.map.qmsg
...\..\SIN.pre_map.cdb
...\..\SIN.pre_map.hdb
...\..\SIN.psp
...\..\SIN.pss
...\..\SIN.rtlv.hdb
...\..\SIN.rtlv_sg.cdb
...\..\SIN.rtlv_sg_swap.cdb
...\..\SIN.sgdiff.cdb
...\..\SIN.sgdiff.hdb
...\..\SIN.signalprobe.cdb
...\..\SIN.sld_design_entry.sci
...\..\SIN.sld_design_entry_dsc.sci
...\..\SIN.syn_hier_info
...\..\SIN.tan.qmsg
...\..\SIN.tis_db_list.ddb
...\SIN
...\SIN.asm.rpt
...\SIN.cdf
...\SIN.done
...\SIN.dpf
...\SIN.fit.rpt
...\SIN.fit.smsg
...\SIN.fit.summary
...\SIN.flow.rpt
...\SIN.map.rpt
...\SIN.map.summary
...\SIN.pin
...\SIN.pof
...\SIN.qpf
...\SIN.qsf
...\SIN.tan.rpt
...\SIN.tan.summary
...\SIN.vhd
...\SIN_assignment_defaults.qdf
    

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