jianfaqi Using hardware description language progr

Title: jianfaqi

Category:
VHDL-FPGA-Verilog
Tags:
File Size:
24kb
Update:
2012-11-26
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0 Times
Uploaded by:
suzhenyu2006

Description: Using hardware description language programming subtraction, and the achievement of the two operands of the subtraction

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To Search: jianfaqi

[addersubtractor] - This is vhdl prepared by the modified in
[add_16_pipe] - 16 pipelined adder, verilog code for the
[Verilog16] - 16-bit adder is needed instead, after a
[add] - Introduced carry_chain_adder, carry_skip
[VHDL-XILINX-EXAMPLE26] - VHDL design of 26 cases of classic - in
[C_to_prepare_multi-media_tools] - TURBO C preparation of multimedia tools,
[StreamSec_Tools_3.0] - StreamSec Tools 3.0 for Delphi 7/2007 Cr
[Flash_ctrl_vhdl_tb] - Prepared by flash controller VHDL source

File list (Check if you may need any files):

jianfaqi
........\cmp_state.ini
........\db
........\..\jianfaqi.db_info
........\..\jianfaqi.eco.cdb
........\..\jianfaqi.sld_design_entry.sci
........\..\jianfaqi_cmp.qrpt
........\..\wed.zsf
........\fullsubstractor.vhd
........\jianfaqi.asm.rpt
........\jianfaqi.done
........\jianfaqi.fit.rpt
........\jianfaqi.fit.summary
........\jianfaqi.flow.rpt
........\jianfaqi.map.rpt
........\jianfaqi.map.summary
........\jianfaqi.pin
........\jianfaqi.qpf
........\jianfaqi.qsf
........\jianfaqi.qws
........\jianfaqi.sim.rpt
........\jianfaqi.tan.rpt
........\jianfaqi.tan.summary
........\jianfaqi.vhd
........\jianfaqi.vwf
........\jianfaqi_assignment_defaults.qdf

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