Description: Verilog language, nios minimum system, tested successfully in the DE2 board
- [VHDLElaborateson100cases.Rar] - VHDL Elaborates on 100 cases. Detailed a
- [pci_core_verilog] - PCI-master s nuclear, verilog language,
- [sine] - Verilog programming, the use of FPGA rea
- [TI_DSP] - TI DSP minimum system schematic is Prote
- [ARM3000] - ARM3000 Fiberxon schematics, as well as
- [asyn_fifo] - asynchronous fifo prepared Verilog sourc
- [EP1C6_EP1C12] - the minimum system of Altera FPGA EP1C6
- [EP2C5] - the minimum system of Altera FPGA EP2C5
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