Description: RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder
- [rs-codec-8-16] - This is a rs decoder running on Verilog
- [RScode] - RS code decoding process, prepared by C,
- [rs-code] - PLD-based encoding and decoding of RS co
- [viterbidecoder] - 2,1,7 convolutional code of viterbi deco
- [Chap16] - This procedure applies to the purchase o
- [C+Csharp+Reader] - CSharp Visual studio window to achieve t
- [animation] - The program is expected to create an avi
- [RSdecoder] - cpld/fpga RS (204,188) decoder of the Ve
File list (Check if you may need any files):
Download