Description: verilog I write by a single pulse generator, through the synthesis and simulation, and variable frequency sine wave generator,
- [systemverilog] - system Verilog Programming
- [pulse-VHDL] - controllable pulse generated VHDL ISE so
- [COUNT100] - a digital counter, every 100 seconds is
- [FPGA_27eg] - FPGA value of the 27 examples. Rar inclu
- [sine] - Verilog programming, the use of FPGA rea
- [timer-counter] - The use of single-chip timer timer funct
- [16_FIR] - 16-order FIR filter - this design USES t
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