- Category:
- SCM
- Tags:
-
[VHDL]
[源码]
- File Size:
- 589.28kb
- Update:
- 2008-10-13
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- Uploaded by:
- wphyl
Description: Verilog prepared using a digital clock, the last paragraph in 8 out digital tube display, for the novice Verilog have some help, is a project file
To Search:
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