Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: myclk Download
 Description: Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.
 Downloaders recently: [More information of uploader 303943243]
 To Search:
  • [LPC-P2378] - Hello I Send this Documet to you
  • [LPC2378_sch_pcb] - Hello I Send you PCB ad SCH of my projec
  • [count10] - Quartus II based on the decimal adder co
File list (Check if you may need any files):
myclk
.....\db
.....\..\myclk.asm.qmsg
.....\..\myclk.cbx.xml
.....\..\myclk.cmp.cdb
.....\..\myclk.cmp.hdb
.....\..\myclk.cmp.logdb
.....\..\myclk.cmp.rdb
.....\..\myclk.cmp.tdb
.....\..\myclk.cmp0.ddb
.....\..\myclk.dbp
.....\..\myclk.db_info
.....\..\myclk.eco.cdb
.....\..\myclk.fit.qmsg
.....\..\myclk.hier_info
.....\..\myclk.hif
.....\..\myclk.map.cdb
.....\..\myclk.map.hdb
.....\..\myclk.map.logdb
.....\..\myclk.map.qmsg
.....\..\myclk.pre_map.cdb
.....\..\myclk.pre_map.hdb
.....\..\myclk.psp
.....\..\myclk.rtlv.hdb
.....\..\myclk.rtlv_sg.cdb
.....\..\myclk.rtlv_sg_swap.cdb
.....\..\myclk.sgdiff.cdb
.....\..\myclk.sgdiff.hdb
.....\..\myclk.sld_design_entry.sci
.....\..\myclk.sld_design_entry_dsc.sci
.....\..\myclk.syn_hier_info
.....\..\myclk.tan.qmsg
.....\myclk.asm.rpt
.....\myclk.done
.....\myclk.fit.rpt
.....\myclk.fit.summary
.....\myclk.flow.rpt
.....\myclk.map.rpt
.....\myclk.map.summary
.....\myclk.pin
.....\myclk.pof
.....\myclk.qpf
.....\myclk.qsf
.....\myclk.qws
.....\myclk.sof
.....\myclk.tan.rpt
.....\myclk.tan.summary
.....\myclk.vhd
    

CodeBus www.codebus.net