Description: 24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
- [shuzizhong] - The design of a can be hours, minutes, s
File list (Check if you may need any files):
Time
....\cmp_state.ini
....\db
....\..\time.asm.qmsg
....\..\time.cbx.xml
....\..\time.cmp.cdb
....\..\time.cmp.hdb
....\..\time.cmp.rdb
....\..\time.cmp.tdb
....\..\time.cmp0.ddb
....\..\time.db_info
....\..\time.eco.cdb
....\..\time.eds_overflow
....\..\time.fit.qmsg
....\..\time.fnsim.cdb
....\..\time.fnsim.hdb
....\..\time.hier_info
....\..\time.hif
....\..\time.map.cdb
....\..\time.map.hdb
....\..\time.map.qmsg
....\..\time.pre_map.cdb
....\..\time.pre_map.hdb
....\..\time.psp
....\..\time.rtlv.hdb
....\..\time.rtlv_sg.cdb
....\..\time.rtlv_sg_swap.cdb
....\..\time.sgdiff.cdb
....\..\time.sgdiff.hdb
....\..\time.signalprobe.cdb
....\..\time.sim.hdb
....\..\time.sim.qmsg
....\..\time.sim.rdb
....\..\time.sim.vwf
....\..\time.sld_design_entry.sci
....\..\time.sld_design_entry_dsc.sci
....\..\time.syn_hier_info
....\..\time.tan.qmsg
....\..\time_cmp.qrpt
....\..\time_sim.qrpt
....\Divider.bdf
....\Divider.bsf
....\fenpin.bdf
....\fenpin.bsf
....\fenpin1m.bsf
....\hour.bdf
....\hour.bsf
....\minute.bdf
....\minute.bsf
....\second.bdf
....\second.bsf
....\test.bdf
....\test.vwf
....\time.asm.rpt
....\time.bdf
....\time.done
....\time.fit.eqn
....\time.fit.rpt
....\time.fit.summary
....\time.fld
....\time.flow.rpt
....\time.map.eqn
....\time.map.rpt
....\time.map.summary
....\time.pin
....\time.pof
....\time.qpf
....\time.qsf
....\time.qws
....\time.sim.rpt
....\time.sof
....\time.tan.rpt
....\time.tan.summary
....\time10.bdf
....\time10.bsf
....\time10.vwf
....\time2.bdf
....\time2.bsf
....\time24.vwf
....\time4.bdf
....\time4.bsf
....\time4.vwf
....\time6.bdf
....\time6.bsf
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