CAN_IP This a IP core of the CAN bus controller wr

Title: CAN_IP

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
60kb
Update:
2012-11-26
Downloads:
1 Times
Uploaded by:
huangyaoguanginhit

Description: This a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.

Downloaders recently: [More information of uploader huangyaoguanginhit]

To Search: can_ip verilog SJA10 ip core MCP2515 veril Verilog IP CAN protocol vhdl CAN BUS verilog sja1000 veril VHDL can protocol in verilog

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File list (Check if you may need any files):

CAN
...\bench
...\.....\verilog
...\.....\.......\can_testbench.v
...\.....\.......\can_testbench_defines.v
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\timescale.v
...\rtl
...\...\verilog
...\...\.......\can_acf.v
...\...\.......\can_bsp.v
...\...\.......\can_btl.v
...\...\.......\can_crc.v
...\...\.......\can_defines.v
...\...\.......\can_fifo.v
...\...\.......\can_ibo.v
...\...\.......\can_register.v
...\...\.......\can_registers.v
...\...\.......\can_register_asyn.v
...\...\.......\can_register_asyn_syn.v
...\...\.......\can_register_syn.v
...\...\.......\can_top.v
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\README.txt

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