DUC XILINX ISE based on frequency of figure design

Title: DUC

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
18kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
wendy_cn

Description: XILINX ISE based on frequency of figure design, use one of the XILINX multiplication IP. Has passed the project practical, easy to use.

Downloaders recently: [More information of uploader wendy_cn]

To Search: duc ise ISE xaw pu DUC veril .ise vhdl duc

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File list (Check if you may need any files):

DUC
...\comp_mul.v
...\comp_mul.xaw
...\comp_mul_add.v
...\comp_mul_add.xaw
...\comp_mul_sub.v
...\comp_mul_sub.xaw
...\DUC.vhd
...\mul_amp.v
...\mul_amp.xaw
...\nco_sinetab.v
...\nco_sinetab.xco
...\Tx_Halfband_Compmul.vhd

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