Title:
FPGAphaselockedloopdesign
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Description: Introduce the application of VHDL technical design embedded DPLL road approach, described in detail its working principle and design idea, and programmable logic device FPGA implementation.
- [pll_improvement] - an improved DPLL design an improved desi
- [adpll] - All-digital phase-locked loop function a
- [DPLL2] - All-digital phase-locked loop circuit de
- [PLL] - Phase-locked loop simulation problem, ca
- [pll_code] - 全数字锁相环的verilog源代码
- [2009] - Intelligent all-digital phase-locked loo
- [255] - All-digital PLL Verilog source code, thr
- [AD-PLL] - DPLL based on VHDL Design and Implementa
File list (Check if you may need any files):
基于FPGA的全数字锁相环设计.pdf
