ADC_INTERFACE it is a verilog code written for MAX

Title: ADC_INTERFACE

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
6kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
the_0_two_00

Description: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.

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File list (Check if you may need any files):

rtl
...\adc_bcd27seg_dec.v
...\adc_clk_div.v
...\adc_interface.v
...\adc_lut.v
...\adc_max186_sm.v
...\adc_top.v

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