Description: Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter
- [FPGA_FIR] - VHDL prepared by the FIR filter source f
- [CICFILTERPROCESS.GZ] - CIC filter simulation program, so will t
- [cic] - Verilog code written by CIC filter proce
- [rr] - Software Radio Research and decimation f
- [cordic] - CIC filter source code, Verilog has writ
- [fft] - With C++ Prepared FFT function, can be u
- [jcxz] - Go to the target server (FTP) to check a
- [cic] - Fifth-order CIC points comb filter, can
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