Title:
ARelativelySimpleRISCCPU Download
Description: A Relatively Simple RISC CPU design source with detailed documentation. ModelSim simulation can be carried out, and they can Synplify synthesis.
- [RISCCore_verilog] - RISC instructions to achieve VerilogHDL
- [MIPS] - The source and design document of
- [CPU_design] - a simple instructions cpu design. 4 can
- [OpenRISC] - an open RISC, has been applied to practi
- [alu] - 16-bit RISC CPU
- [controlunit] - CPU design controlunit source, which com
- [synplify] - Chinese Huawei Synplify Tutorial
- [risc] - Source embedded RISC processors, includi
- [risc] - 6 bits risc cpu by Verilog
File list (Check if you may need any files):