Description: VHDL language used to write the procedure that contains the following functions: 1. Keyboard scan 2. Control of AD converters 3. Generate PWM signals with the 51 series CPU interface, and then in the address data bus 51, the single-chip by visiting the address bus data Register to control the CPLD
- [equlizer] - equalizer communications channel anti-in
- [pll1218] - with a DPLL CPLD, VHDL or V language.
- [hd_driver] - hard drives example, the basic system-dr
- [cpldTo8051] - CPLD and 8051 bus interface VHDL design
- [keyscan] - 4 × 4 keyboard scan Verilog code, the CP
- [PWM_DCmotorControl] - The VHDL-based DC motor PWM control proc
- [USBblaster] - Altera Corporation debugging CPLD/FPGA u
- [5050PWM_V54] - FPGA-based ISA interface 3 Road encoder
- [CPLD_Design_50] - 50 cases of practical CPLD design, very
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