Description: Use Quartus II to design FPGA application design examples
"\ Example-b3-1\uart_regs\ SRC" directory is the design source file
"\ Example-b3-1\uart_regs\ core" is the IP macro function module of Altera
The "\ Example-b3-1\uart_regs\sim\ funcsim" directory is the function simulation file
The "\ Example-b3-1\uart_regs\sim\ parsim" directory is the sequence simulation file
Under the directory of "\ Example-b3-1\uart_regs\ dev", the project files (including the process files and result files of the constraint, synthesis, layout wiring)
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