Description: EDA experiment -UART serial port experiment: UART consists of data bus interface, control logic, baud rate generator, sending part and receiving part. UART transmitter
The transmitter is output 1 bit every 16 CLK16 clock cycles, followed by a starting position, 8 bits (assuming the data bit is 8 bits), 1 bit checkbit (optional), and 1 stop bit.
The UART receiver
- the serial data frame and the receiving clock are asynchronous, and the data sent from logic 1 to logic 0 can be regarded as the beginning of a data frame. Receiver to capture the start bit, first determine the RXD input from 1 to 0, logic 0 to 8 CLK16 clock cycle, is the normal starting, then 16 CLK16 in every clock cycle sampling receives the data, the displacement input shift register RSR, the final output data dout. Also output a data receive flag signal data reception.
Baud rate generator
- the receiving and sending of UART is sent and received according to the same baud rate. Baud rate generator to generate the clock frequency is not baud rate clock frequency, but the baud rate clock frequency of 16 times, the purpose is to be the time for receiving a precise sampling, with asynchronous serial data is put forward.
- the baud rate is calculated according to the given crystal clock and the required baud rate.
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